Typically, processors are constructed from a variety of very large scale integrated circuit (VLSI) chips used as building blocks in an architecture which can be divided into two components; an instruction processor that supervises the order and decoding of instructions to be executed, and a data processor which performs the operations called for by the instructions on the data. These components are often two different chips mounted on a circuit board, or can be fabricated on a single chip in two dimensional geometry. The instruction processor normally includes a program memory which contains instructions. Each instruction includes a plurality of bits to control the elements within the data processor. In addition, the controller is used to issue addresses that are applied to the program memory to access the instruction sequence to be executed. It is desirable to execute these instructions as fast as possible, preferably in one clock cycle or less. However, due to the geometry of laying out the microprocessor using existing methods, the difficulties in increasing speed also increase the cost and complexity of manufacturing.
Data processors have been categorized as either an 8, 16 or 32-bit device. They are capable of performing arithmetic or logic operations on 8, 16, or 32 bits, respectively. Some processors have limited ability to perform operations on a full-sized word. For example, a 16-bit data processor may be able to perform operations on the least-significant byte (8 bits) of a full-sized 16-bit word. In one such approach, a 16-bit processor is formed from a parallel combination of four-bit processors. This approach is typically referred to as the xe2x80x9cbit-slicedxe2x80x9d technique.
This method entails extensive parallel interconnection of the terminal pins of the data processor chips. Additionally, space, is at a premium on the printed circuit board used to mount the micro-processor chips and is consumed by the data processor chips and the busses used to connect the chips.
While previous 8- and 16-bit data processors have been available using bipolar semiconductor fabrication techniques, 32-bit data processors have used a slower metal oxide silicon fabrication procedure. Also contributing to speed degradation, previous processors used a single multiplexed input/output bus, which typically imposed limits on input and output operation.
The components of each chip are typically made from thousands of transistors and inverters. These elements are used to form gate arrays, shift registors, memories and other components. The speed of operation of the data processor, and therefore the microprocessor itself, depends in large part on the architecture of its internal circuitry. Throughput (the time it takes for an instruction to be executed) depends, in part, upon the number of gates data must pass through during its processing. Also, operating speed can be increased by combining several operations into one instruction. A continuing need exists however to provide hardware capable of faster throughput where a larger number of instructions can be executed within the cycle time of the device and at the same time provide such a structure in a smaller space that is dependable, relatively inexpensive and is constructed using the simplest fabrication procedure possible.
The present invention relates to the structure and fabrication of very large scale integrated circuits, and in particular, to vertically stacked and interconnected circuit elements for data processing, control systems, and programmable computing. A preferred embodiment involves a microprocessor divided into functional blocks, for instance, an Arithmetic Logic Unit (ALU), a controller, memory elements etc., which are fabricated in the same or separate semiconductor wafers and then stacked. Typically, the functional blocks communicate with one another using address, data and control busses. These busses consist of a number of metal wires that are normally routed along the surface of a silicon chip. Typically, the metal wires run in areas of the chip between the functional blocks and take up a considerable amount of real estate, perhaps as much as half that available. In the present invention the functional blocks of the circuit are divided into two or more sections with one section of the circuit on a bulk chip and the remaining blocks on an overlying thin film with components electrically connected through an intervening insulating layer.
Both bulk and thin film semiconductor layers can be incorporated into preferred embodiments of the invention. Circuits can be formed in bulk silicon, silicon-on-insulator (SOI) structures, or in III-V materials such as gallium arsenide, or in composite structures including bulk Si, SOI, and/or thin film GaAs. The various layers of the device can be stacked using an insulating layer that bonds the layers together and conductive interconnects or vertical busses extending through the insulating layer which preferably comprises a polymeric material such as an adhesive. Thermal and electrical shielding can be employed between adjacent circuit layers to reduce or prevent thermal degradation or cross-talk.
Wire bond pads on the bulk chip or on the thin film layers of the structure are required for communicating with the package the chips will be placed in such as a leadless chip carrier. These pads need to be large enough that wires can be bonded to them. Interconnection pads are used to connect the different layers of the circuit together. These pads can be considerably smaller than the wire bond pads because the method of interconnection will, in a preferred embodiment, be through metal deposition. Complementary pairs of interconnection pads are used on the bulk and SOI chips. Instead of running busses along the surface of the wafer, many of these run in a vertical direction (the third dimension) between functional blocks freeing up significant real estate for active circuitry.
In a preferred embodiment, after fabricating the different layers of the circuit, the SOI circuit layers can be transferred to the bulk silicon chip. The transfer is conducted using an electrically insulating adhesive layer between the bulk and SOI chips to secure the two circuit layers together and at the same time maintain the electrical isolation required. In addition, in an embodiment using a single transfer process the isolation oxide layer of the SOI material is the upper most layer on the combined chip. This completely isolates the active circuitry from the surface of the wafer, allowing routing of metal wires across the surface. Since an interconnection metal layer completes the circuit, this same metal layer is used for busses without losing valuable circuit space on each layer. To perform the interconnection, vias are cut down to the interconnection pads on the bulk chip or underlying thin film semiconductor circuit layer. Metal deposition is used to connect the lower and upper functional blocks.
Some of the advantages of this three dimensional approach include higher speed and packing density. The speed increases result from at least two areas; the first is the reduction in the length of the busses. On chip circuit speed is limited to some extent by the length of the wires carrying signals around the chip. All wires on the chip have associated capacitances and inductances. Typical treatment of wire lead delays follows from simple transmission line analysis. The longer the leads, the longer the associated delays. In the proposed approach, shorter busses will result in smaller delays and higher speed circuit performance.
The second source of speed improvement is obtained from the SOI itself. The circuit is divided into two halves or into three or more layers in other embodiments. In one embodiment, the first half is a bulk circuit. However, this silicon circuitry can be entirely replaced on SOI.
Improvement in operating speed for SOI circuitry originates from three areas. Perhaps the largest speed enhancement results from the fact the circuit is isolated from the bulk silicon wafer by a thick oxide layer. This reduces individual device capacitance as well as the capacitance associated with the metal and substrate. A second reduction in capacitance is achieved due to a reduction in the exposed source and drain areas common in CMOS circuit components. This is a result of the fact that in SOI, the source/drain implantations are terminated by the oxide layer. This eliminates a large portion of the capacitance associated with the source/drain to well junctions. The final increase in speed has been reported using thin film SOI devices. These are fabricated in silicon layers having thickness in the range of 0.1-10 xcexcm and preferably in 1.0 xcexcm or less of silicon. As indicated previously the bulk or thin film layers of semiconductor material can also utilize III-V materials such as GaAs made using standard chemical vapor deposition process.
Increases in packing density come from two sources. The three dimensional approach allows stacking fractions of the circuit on top of one another. The two layer stack without any other modification already consumes half the area of the standard 2D circuit. A second increase is available due to the reduction of area needed to route the busses over the chip. This will again halve the area of the combined circuit leading to a minimum packing density decrease of 4 times.
In one embodiment blocks requiring higher speeds are fabricated in the SOI for instance. A second alterative is to divide the microprocessor into four bit processors that are combined in two layers to create an 8 bit microprocessor or in four layers to create a 16 bit microprocessor. The embodiments employ various interconnection pad configurations. In one embodiment, for instance, the pads on the upper and lower circuits are offset slightly. This allows individual vias to be etched down to each. Deposited metal then interconnects the two pads. Alignment tolerances determine the pad size needed.
In one embodiment test devices are included in the SOI mask set. These allow probing individual devices to determine their performance. The test chip includes small test circuits which provide information on circuit performance parameters such as ring oscillators and gate delay chains. An extra metal layer can be used in order to route the small interconnection pads out to larger pads for testing.
Having completed and tested each of the circuit layers which make up the complete microprocessor, the SOI circuit is transferred to the bulk wafer. A key aspect of the transfer process is that the two or more circuit layers must be aligned to one another. A second aspect of this task is that once combined the circuit halves are integrated. This is performed by etching via holes down to the appropriate interconnection pads, depositing aluminum and patterning the aluminum to create interconnection between the circuits and any routing that may be required.
In embodiments employing more than two layers, interconnections can be performed after transfer of each successive layer or after two or more layers. Such connections can be optical or electrical, and can run externally or through the bonding layers connecting each layer. Connections can also be made between circuit elements on the same layer or different layers using a circuit routing layer. The circuit routing layer can also have circuitry thereon or can be made of an electrical or thermal insulating material such as ceramic or silicon carbide. The circuit routing layer has metalization lines or busses formed on one or both sides. In non-active regions the circuit routing layer can be patterned on one or both sides with a metal that can be connected to ground for further insulation between layers.
A double transfer process can also be used in which a thin film has circuits fabricated followed by transfer onto a second disposable or reusable substrate, back processing of the circuit layer as needed and then transfer onto the stacked structure and interconnecting metalization. Tiling of transferred thin film circuits on each layer of the device can also be employed. These transfer and tiling methods can be used to incorporate optoelectronic components including light emitting diodes (LEDs) and displays into the three dimensional structure.